Kin-Sing Lee Email
Principal MTS Silicon Design Engineer @ AMD
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Kin-Sing Lee Location
- Markham, ON, CA
Kin-Sing Lee Work
- 2024 -now Principal MTS Silicon Design Engineer @
- 2019 -2024 Manager Silicon Design Engineer @
- 2016 -2019 MTS ASIC and Layout Design Engineer @
- 2012 -2016 Senior ASIC and Layout Design Engineer @
- 2011 -2012 ASIC and Layout Design Engineer II @
- 2008 -2011 Senior Foundry Engineer @ Microsemi Corporation (formerly Actel Corporation)
- 2006 -2007 Engineering Intern @ Microsemi Corporation (formerly Actel Corporation)
Kin-Sing Lee Education
- University of Toronto
Master’s Degree (Computer Engineering)
2013-2017 - University of Toronto
Bachelor (Electrical Engineering)
2003-2008
Kin-Sing Lee Skills
- Verilog
- Perl
- Primetime
- C
- C++
- Programming Languages
- JMP
- Microsoft Excel
- PowerPoint
- Microsoft Word
- SoC
- Semiconductors
- IC
- Debugging
- RTL design
- Static Timing Analysis
- FPGA
- JTAG
- Cadence Virtuoso
Kin-Sing Lee Summary
- Kin-Sing Lee, based in Markham, ON, CA, is currently a Principal MTS Silicon Design Engineer at AMD. Kin-Sing Lee brings experience from previous roles at AMD. Kin-Sing Lee holds a 2013 - 2017 Master’s Degree in Computer Engineering @ University of Toronto. With a robust skill set that includes Verilog, Perl, Primetime, C, C++ and more. Kin-Sing Lee has 3 emails on RocketReach.
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