Kelin Chen Email
Director, IC engineering @ NeuHelium
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Kelin Chen Location
- Shanghai, China
Kelin Chen Work
- 2019 -now Director, IC engineering @
- 2016 -2019 Director, ASIC design @ a startup company
- 2013 -2016 IC5 ASIC design engineer @
- 2010 -2013 staff ASIC design engineer, project leader @
- 2007 -2010 senior ASIC design engineer @
- 2006 -2007 senior SOC design engineer @
- 2004 -2006 project leader, team leader @ chipsea
Kelin Chen Education
- 南京大学
master (semiconductor physics)
1998-2001 - Nanjing University
bachelor (semiconductor physics)
1995-1998
Kelin Chen Skills
- Static Timing Analysis
- Timing Closure
- ASIC
- SoC
- RTL design
- Logic Synthesis
- Logic Design
- Debugging
- DFT
- Integrated Circuit Design
- FPGA
- chip level ASIC design
- SERDES
- Simulations
- JTAG
- Microarchitecture
- IC
- Verilog
- Timing
- VLSI
- Low-power Design
- EDA
- RTL coding
- Digital Signal Processors
- Analog
- SystemVerilog
- Functional Verification
- PCIe
- CMOS
- Social Media
- Graphic Design
- Strategic Planning
- Java
- Design
- Low Power Design
- Services
- Asic Design
Kelin Chen Summary
- Kelin Chen, based in Shanghai, China, is currently a Director, IC engineering at NeuHelium. Kelin Chen brings experience from previous roles at a startup company, NVIDIA and LSI Logic. Kelin Chen holds a 1998 - 2001 master in semiconductor physics @ 南京大学. With a robust skill set that includes Static Timing Analysis, Timing Closure, ASIC, SoC, RTL design and more. Kelin Chen has 2 emails on RocketReach.
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