Kedar Patel's Location
San Jose, CA, US
Kedar Patel's Work
- Staff Product Engineer @ Power Integrations
- Staff Product Engineer @ Navitas Semiconductor
- Senior Product Evaluation Engineer @ onsemi
Kedar Patel's Education
- San Jose State University
MS (Electrical Engineering)
2009 - 2011 - institute of Technology, Nirma University
B.Tech (Electronics and Communication Engineering)
2005 - 2009
Kedar Patel's Skills
- Hardware Architecture
- Cadence Virtuoso
- Analog Circuit Design
- Load Testing
- Debugging
- Evaluations
- RTL design
- Matlab
- PCB design
- Analog
Kedar Patel's Summary
Kedar Patel, based in San Jose, CA, US, is currently a Staff Product Engineer at Power Integrations, bringing experience from previous roles at Navitas Semiconductor, ON Semiconductor and BatchTest Systems. Kedar Patel holds a 2009 - 2011 MS in Electrical Engineering @ San Jose State University. With a robust skill set that includes Hardware Architecture, Cadence Virtuoso, Analog Circuit Design, Load Testing, Debugging and more, Kedar Patel contributes valuable insights to the industry. Kedar Patel has 3 emails on RocketReach.
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