Kavyesh Talwar Email & Phone Number
Senior RTL Design Engineer @ Anthriq
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Kavyesh Talwar Location
- Bengaluru, KA, IN
Kavyesh Talwar Work
- Senior RTL Design Engineer @ (July 2026 - Present)
- RTL Design Engineer @ (July 2023 - July 2026)
- Design Verification Intern @ (January 2023 - June 2023)
- Analog Intern @ Texas Instruments (May 2022 - July 2022)
- Research Intern @ (May 2020 - June 2020)
Kavyesh Talwar Education
- Birla Institute of Technology and Science, Pilani
Bachelor of Engineering - BE (Electrical and Electronics Engineering)
2018-2023 - Birla Institute of Technology and Science, Pilani
Msc (Physics)
2018-2023
Kavyesh Talwar Skills
- Universal Verification Methodology (UVM)
- Computer Architecture
- SystemVerilog
- Verilog HDL
- Python (Programming Language)
- Verdi
- C++
- Digital Circuit Design
- Analog Circuit Design
- Semiconductors
- Research
- Circuit Design
- Engineering
- MATLAB
- Microsoft Office
- C (Programming Language)
- Communication
- Leadership
- COMSOL
- Electronics
- APB
- AXI
- Application-Specific Integrated Circuits (ASIC)
- DDR6
- Debugging
- Dynamic Random-Access Memory (DRAM)
- Low-power Design
- Memory Controllers
- Microarchitecture
- Primetime
- RTL Design
- Simvision
- Synopsys Primetime
- System on a Chip (SoC)
- TCL
- Unified Power Format (UPF)
- Verilog
- Very-Large-Scale Integration (VLSI)
Kavyesh Talwar Summary
- Kavyesh Talwar, based in Bengaluru, KA, IN, is currently a Senior RTL Design Engineer at Anthriq. Kavyesh Talwar brings experience from previous roles at Google, NVIDIA, Texas Instruments and Indira Gandhi Centre for Atomic Research (IGCAR). Kavyesh Talwar holds a 2018 - 2023 Bachelor of Engineering - BE in Electrical and Electronics Engineering @ Birla Institute of Technology and Science, Pilani. With a robust skill set that includes Universal Verification Methodology (UVM), Computer Architecture, SystemVerilog, Verilog HDL, Python (Programming Language) and more. Kavyesh Talwar has 3 emails and 1 mobile phone numbers on RocketReach.
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Kavyesh Talwar
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