Kavya Setty Email & Phone Number
Physical Design Engineer @ Google
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Kavya Setty Location
- Sunnyvale, CA, US
Kavya Setty Work
- 2018 -now Physical Design Engineer @
- 2014 -2018 SoC Design Engineer @
- 2014 -2014 Graduate Technical Intern- SoC Integration Engineer @
- 2012 -2014 Graduate Student @
- 2012 -2012 Intern @
Kavya Setty Education
- University of Southern California
Master's degree (Electrical Engineering)
2012-2014 - BNM Institute Of Technology
Bachelor of Engineering (BEng) (Electrical, Electronics and Communications Engineering)
2008-2012
Kavya Setty Skills
- Verilog
- VHDL
- Cadence Virtuoso
- C++
- ModelSim
- Perl
- Functional Verification
- Xilinx ISE
- Cadence NC-Verilog
- Simulations
- Compilers
- Chipscope Pro
- Synopsys Primetime
- SystemVerilog
- System Verilog
- Design Compiler
- QuestaCDC
- Clock Domain Crossing
- Computer Architecture
- VLSI
- SoC
- ASIC
- RTL Design
- FPGA
- Cadence Nc Verilog
- Ic Compiler 1 &2
- Formality
Kavya Setty Summary
- Kavya Setty, based in Sunnyvale, CA, US, is currently a Physical Design Engineer at Google. Kavya Setty brings experience from previous roles at Intel Corporation, University of Southern California and Indian Institute of Science. Kavya Setty holds a 2012 - 2014 Master's degree in Electrical Engineering @ University of Southern California. With a robust skill set that includes Verilog, VHDL, Cadence Virtuoso, C++, ModelSim and more. Kavya Setty has 4 emails and 2 mobile phone numbers on RocketReach.
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