Bachelor of Engineering (BEng) (Electrical, Electronics and Communications Engineering)
2008-2012
Kavya Setty Skills
ASIC
C++
Cadence NC-Verilog
Cadence Virtuoso
Clock Domain Crossing
Compilers
Computer Architecture
Design Compiler
FPGA
Formality
Functional Verification
IC Compiler 1 &2
ModelSim
Perl
QuestaCDC
RTL Design
Simulations
SoC
Synopsys Primetime
System on a Chip (SoC)
VHDL
VLSI
Verilog
Xilinx ISE
Chipscope Pro
SystemVerilog
System Verilog
Cadence Nc Verilog
Kavya Setty Summary
Kavya Setty, based in Sunnyvale, CA, US, is currently a Physical Design Engineer at Google. Kavya Setty brings experience from previous roles at Intel Corporation, University of Southern California and Indian Institute of Science. Kavya Setty holds a 2012 - 2014 Master's degree in Electrical Engineering @ University of Southern California. With a robust skill set that includes ASIC, C++, Cadence NC-Verilog, Cadence Virtuoso, Clock Domain Crossing and more. Kavya Setty has 5 emails and 2 mobile phone numbers on RocketReach.
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