Kavitha Velayudhan's Location
Singapore
Kavitha Velayudhan's Work
- ASIC Layout Engineer @ Uni Connect
- Research Associate @ NBS Alumni Affairs, NTU
- Senior Project Engineer @ Wipro
Kavitha Velayudhan's Education
- Birla Institute of Technology and Science, Pilani
Master of Science - MS (Microelectronics)
2010 - 2012 - Cochin University of Science and Technology, India
Bachelor of Technology (B.Tech.) (Electronics & Communication Engineering)
- Birla Institute of science and Technology, Pilani, India
Master of Science (MS) (Microelectronics)
Kavitha Velayudhan's Skills
- Physical Design
- Drc/Lvs/Pex Using Calibre
- ASIC
- Static Timing Analysis
- Cadence Virtuoso Layout Editor
- Cadence Virtuoso
- SoC
- VLSI
- Very Large Scale Integration Vlsi
- TCL
Kavitha Velayudhan's Summary
Kavitha Velayudhan, based in Singapore, is currently a ASIC Layout Engineer at Uni Connect Pte Ltd, bringing experience from previous roles at Nanyang Technological University Singapore and Wipro Technologies. Kavitha Velayudhan holds a 2010 - 2012 Master of Science - MS in Microelectronics @ Birla Institute of Technology and Science, Pilani. With a robust skill set that includes Physical Design, Drc/Lvs/Pex Using Calibre, ASIC, Static Timing Analysis, Cadence Virtuoso Layout Editor and more, Kavitha Velayudhan contributes valuable insights to the industry. Kavitha Velayudhan has 1 email on RocketReach.
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