Kathy Peng's Location

Saratoga, CA, US

Kathy Peng's Work

  • Staff Design Engineer @ SEEQ Technology
  • Design Engineer @ Fujitsu
  • Design Engineer @ Sumsung

Kathy Peng's Education

  • Oregon State University

    MSEE

  • Peking University

    BS/MS (Physics)

Kathy Peng's Skills

  • Semiconductors
  • ASIC
  • PLL
  • Analog Circuit Design
  • Analog
  • Mixed Signal
  • CMOS
  • Circuit Design
  • Cadence Virtuoso
  • Verilog

Kathy Peng's Summary

Kathy Peng, based in Saratoga, CA, US, is currently a Senior Staff Design Engineer at Intel, bringing experience from previous roles at nSerial, LSI Corporation, SEEQ Technology and Fujitsu Semiconductor. Kathy Peng holds a MSEE @ Oregon State University. With a robust skill set that includes Semiconductors, ASIC, PLL, Analog Circuit Design, Analog and more, Kathy Peng contributes valuable insights to the industry. Kathy Peng has 3 emails on RocketReach.

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