Kapil Narula Email & Phone Number
Senior Principal Engineer @ NXP Semiconductors
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Kapil Narula Location
- Austin, TX, US
Kapil Narula Work
- Senior Principal Engineer @ (April 2021 - Present)
- DFT Enginner @ (April 2017 - Present)
- DFT Enginner @ (January 2011 - March 2017)
- Physical Design Engineer @ (July 2006 - July 2009)
Kapil Narula Education
- North Carolina State University
MS (Computer Engineering)
2009-2010
Kapil Narula Skills
- VLSI
- ASIC
- Place & Route
- Clock Tree Synthesis
- Physical Design
- RTL design
- SystemVerilog
- Static Timing Analysis
- Verilog
- Timing Closure
- Low-power Design
- Functional Verification
- SoC
- Logic Design
- Computer Architecture
- Cadence Virtuoso
- EDA
- DFT
- RTL coding
- TCL
- Very-Large-Scale Integration (VLSI)
- Place and Route
- Low Power Design
- Very Large Scale Integration Vlsi
- Very Large Scale Integration
Kapil Narula Summary
- Kapil Narula, based in Austin, TX, US, is currently a Senior Principal Engineer at NXP Semiconductors. Kapil Narula brings experience from previous roles at NXP Semiconductors, Intel Corporation and Freescale Semiconductor. Kapil Narula holds a 2009 - 2010 MS in Computer Engineering @ North Carolina State University. With a robust skill set that includes VLSI, ASIC, Place & Route, Clock Tree Synthesis, Physical Design and more. Kapil Narula has 2 emails and 1 mobile phone numbers on RocketReach.
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