Kanur Aneja's Location

San Jose, CA, US

Kanur Aneja's Work

  • Wireless SOC Design Verification Engineer @ Apple
  • Senior Design Verification Engineer @ AMD
  • Design Verification Engineer @ AMD

Kanur Aneja's Education

  • San Jose State University

    Masters (Electrical Engineering)

    2010 - 2012
  • Punjab Engineering College

    Bachelors (Electrical Engineering)

    2006 - 2010
  • Carmel Convent School

    1994 - 2004

Kanur Aneja's Skills

  • Computer Architecture
  • Mechatronics
  • ModelSim
  • Verilog
  • System Verification
  • C++
  • Xilinx FPGA
  • Synopsys
  • ASIC
  • SoC

Kanur Aneja's Summary

Kanur Aneja, based in San Jose, CA, US, is currently a Wireless SOC Design Verification Engineer at Apple, bringing experience from previous roles at AMD, Marvell Semiconductor and Texas Instruments. Kanur Aneja holds a 2010 - 2012 Masters in Electrical Engineering @ San Jose State University. With a robust skill set that includes Computer Architecture, Mechatronics, ModelSim, Verilog, System Verification and more, Kanur Aneja contributes valuable insights to the industry. Kanur Aneja has 4 emails and 1 mobile phone number on RocketReach.

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