K Saikumar Email
Senior RTL Design Engineer @ ChipSilica (formerly NexSilica)
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K Saikumar Location
- Hyderabad, IN
K Saikumar Work
- 2026 -now Senior RTL Design Engineer @
- 2024 -now RTL Design Engineer @
- 2022 -2024 RTL Engineer @
- 2021 -2022 Trainee @
K Saikumar Education
- Mavensilicon
Vlsi training (Asic and verification engineer)
2020-2021 - Geethanjali College of Engineering and Technology
Bachelor of Technology - BTech (Electrical, Electronics and Communications Engineering)
2016-2020
K Saikumar Summary
- K Saikumar, based in Hyderabad, IN, is currently a Senior RTL Design Engineer at ChipSilica. K Saikumar brings experience from previous roles at SmartSoC Solutions Pvt Ltd and Capgemini Engineering. K Saikumar holds a 2020 - 2021 Vlsi training in Asic and verification engineer @ Mavensilicon. K Saikumar has 1 emails on RocketReach.
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