Jyotsna Chauhan Email & Phone Number
Physical Design Engineer @ NVIDIA
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Jyotsna Chauhan Location
- California, United States
Jyotsna Chauhan Work
- Physical Design Engineer @ (June 2022 - Present)
- Engineer @ (September 2019 - June 2022)
- Senior Physical Design Engineer @ (June 2013 - June 2019)
- Senior Process Engineer @ (June 2012 - June 2013)
- Project Engineer @ (January 2006 - January 2007)
Jyotsna Chauhan Education
- University of Florida
Doctor of Philosophy (Philosophy)
2008-2012 - National Institute of Technology, Hamirpur
Bachelor of Technology (Electronics, Engineering, Communications)
2002-2006
Jyotsna Chauhan Skills
- Matlab
- Numerical Analysis
- IC
- Simulations
- Semiconductor Device Physics
- Device Modeling
- Semiconductor Device
- CMOS
- Quantum Transport Theory
- Digital Circuit Design
- C++
- Cadence Virtuoso
- Testing
- Perl
- ICC
- Synopsys Primetime
- RV
- Verilog
- ASIC
- Semiconductors
- VHDL
- Electronics
- Linux
- Yield
- Debugging
- Embedded Systems
- VLSI
- Design of Experiments
- C
- Design
Jyotsna Chauhan Summary
- Jyotsna Chauhan, based in California, United States, is currently a Physical Design Engineer at Nvidia. Jyotsna Chauhan brings experience from previous roles at Apple, Intel Corporation and Wipro. Jyotsna Chauhan holds a 2008 - 2012 Doctor of Philosophy in Philosophy @ University of Florida. With a robust skill set that includes Matlab, Numerical Analysis, IC, Simulations, Semiconductor Device Physics and more. Jyotsna Chauhan has 2 emails and 2 mobile phone numbers on RocketReach.
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