Justin Reyes's Location
Santa Clara, California, United States
Justin Reyes's Work
- SOC Design Engineer @ Intel Capital
- Microarchitect @ Intel Capital
- IP Logic Design Engineer @ Intel Capital
- Component Design Engineer @ Intel Capital
- Component Engineer @ Northrop Grumman
- Computer Support Technician @ USC Information Technology Services (ITS)
- Supply Chain Engineer Intern @ Northrop Grumman
Justin Reyes's Education
- University of Southern California
MSEE (Electrical Engineering)
2009 - 2010 - University of Southern California
BSEE (Electrical Engineering)
2005 - 2009
Justin Reyes's Skills
- SystemVerilog
- RTL design
- Verilog
- Unix
- ModelSim
- Computer Architecture
- Xilinx
- VLSI
- Linux
- RTL coding
Justin Reyes's Summary
Justin Reyes, based in Santa Clara, California, United States, is currently a SOC Design Engineer at Intel Corporation, bringing experience from previous roles at Intel Corporation and Northrop Grumman Aerospace Systems. Justin Reyes holds a 2009 - 2010 MSEE in Electrical Engineering @ University of Southern California. With a robust skill set that includes SystemVerilog, RTL design, Verilog, Unix, ModelSim and more, Justin Reyes contributes valuable insights to the industry. Justin Reyes has 3 emails on RocketReach.
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