Joy Paul Email & Phone Number
Senior Staff Engineer (Full chip timing lead and Physical Design Engineer for E-Core CPU) @ Intel Corporation
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Joy Paul Location
- Austin, TX, US
Joy Paul Work
- 2023 -now Senior Staff Engineer (Full chip timing lead and Physical Design Engineer for E-Core CPU) @
- 2013 -2023 Staff Engineer (Full chip timing lead and Physical Design Engineer for E-Core Processor) @
- 2006 -2013 Senior Component Design Engineer (Full Chip Timing Lead) @
- 2000 -2006 Staff Engineer @
- 1999 -2000 Circuit Design Engineer @ Compaq Computer Corporation
Joy Paul Education
- Oklahoma State University
Master of Science (MS) (Electrical and Electronics Engineering)
1997-1998
Joy Paul Skills
- Semiconductors
- Processors
- VLSI
- Microprocessors
- Primetime
- Debugging
- SoC
- Intel
- ASIC
- Low-power Design
- EDA
- Physical Design
- Static Timing Analysis
- Verilog
- DFT
- IC
- Timing Closure
- Timing
- Design
- Component Design
- Low Power Design
Joy Paul Summary
- Joy Paul, based in Austin, TX, US, is currently a Senior Staff Engineer (Full chip timing lead and Physical Design Engineer for E-Core CPU) at Intel Corporation. Joy Paul brings experience from previous roles at Intel Corporation, IBM and Compaq Computer Corporation. Joy Paul holds a 1997 - 1998 Master of Science (MS) in Electrical and Electronics Engineering @ Oklahoma State University. With a robust skill set that includes Semiconductors, Processors, VLSI, Microprocessors, Primetime and more. Joy Paul has 5 emails and 1 mobile phone numbers on RocketReach.
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