Jongseok Lee Email & Phone Number
Silicon Design Engineer @ Altera
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Jongseok Lee Location
- San Jose, CA, US
Jongseok Lee Work
- 2025 -now Silicon Design Engineer @
- 2024 -2025 FPGA IP Engineer @
- 2021 -2024 FPGA IP Engineer @
- 2018 -2021 Sr. Digital Design Engineer @
- 2016 -2018 FPGA Design Engineer @
- 2016 -2016 Digital Logic Design Intern @ KMW COMMUNICATION USA.
Jongseok Lee Education
- University of Southern California
Master of Science - MS (Electrical Engineering)
2014-2016 - Sejong University 2013
Jongseok Lee Summary
- Jongseok Lee, based in San Jose, CA, US, is currently a Silicon Design Engineer at Altera. Jongseok Lee brings experience from previous roles at Altera, Intel Corporation, TDK InvenSense and VLNComm. Jongseok Lee holds a 2014 - 2016 Master of Science - MS in Electrical Engineering @ University of Southern California. Jongseok Lee has 3 emails and 1 mobile phone numbers on RocketReach.
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