Jonathan Tung Email

MTS Silicon Design Engineer @ AMD

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Jonathan Tung Location

Newmarket, ON, CA

Jonathan Tung Work

2020 - now MTS Silicon Design Engineer @ AMD
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2019 - 2020 Principal Asic Engineer @ Cadence Design Systems
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2016 - 2019 Lead Asic Engineer @ Cadence Design Systems
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2011 - 2015 Product Design Engineer @ PMC-Sierra is now Microsemi
2010 - 2011 Asic Design Engineer @ Wavesat
2007 - 2009 Asic Design Engineer @ InterDigital, Inc.
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2006 - 2006 Asic and DSP Intern @ InterDigital, Inc.

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Jonathan Tung Education

McGill University
Bachelors (Electrical Engineering)
2002 - 2007

Jonathan Tung Summary

Jonathan Tung, based in Newmarket, ON, CA, is currently a MTS Silicon Design Engineer at Amd. Jonathan Tung brings experience from previous roles at Cadence Design Systems, PMC-Sierra and Wavesat. Jonathan Tung holds a 2002 - 2007 Bachelors in Electrical Engineering @ McGill University. Jonathan Tung has 2 emails on RocketReach.

Jonathan Tung Emails

Found 2 emails

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