Jonathan Lopez-Morell's Location

Elk Grove, CA, US

Jonathan Lopez-Morell's Work

Jonathan Lopez-Morell's Education

  • Michigan State University

    PhD (Electrical Engineering)

    2001 - 2004
  • Michigan State University

    MS (Electrical Engineering)

    1999 - 2001
  • University of Puerto Rico - Mayaguez Campus (RUM)

    BS (Electrical Engineering)

    1994 - 1999

Jonathan Lopez-Morell's Skills

  • Low-power Design
  • Static Timing Analysis
  • Semiconductors
  • Timing Closure
  • Microprocessors
  • Logic Synthesis
  • VLSI
  • Cadence
  • ASIC
  • Verilog

Jonathan Lopez-Morell's Summary

Jonathan Lopez-Morell, based in Elk Grove, CA, US, is currently a Design Engineering Manager; Hiring Manager at Intel Corporation, bringing experience from previous roles at Intel Corporation, Iglesia de Dios Sacramento and Michigan State University. Jonathan Lopez-Morell holds a 2001 - 2004 PhD in Electrical Engineering @ Michigan State University. With a robust skill set that includes Low-power Design, Static Timing Analysis, Semiconductors, Timing Closure, Microprocessors and more, Jonathan Lopez-Morell contributes valuable insights to the industry. Jonathan Lopez-Morell has 2 emails on RocketReach.

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