John Sizer Email & Phone Number
Physical Design Manager @ Hewlett Packard Enterprise
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John Sizer Location
- Eau Claire, WI, US
John Sizer Work
- 2020 -now Physical Design Manager @
- 2020 -now Master Technologist @
- 2019 -2020 Senior Physical Design Engineer @
- 2013 -2019 Sr Design Engineer @
- 2009 -2013 Sr. Engineer @ Open-Silicon
- 1997 -2009 Sr. Engineer @
- 1993 -1997 Design Verification Engineer @
- 1988 -1993 Technical Lead - Systems Test @
John Sizer Skills
- Floorplanning
- Communications
- Debugging
- Functional Verification
- RTL design
- Intel
- ASIC
- Verilog
- Formal Verification
- TCL
- SoC
- EDA
- Primetime
- Timing Closure
- SystemVerilog
- Semiconductors
- Physical Design
- Design
- Static Timing Analysis
- Clock Tree Synthesis
- IC
John Sizer Summary
- John Sizer, based in Eau Claire, WI, US, is currently a Physical Design Manager at Hewlett Packard Enterprise. John Sizer brings experience from previous roles at Hewlett Packard Enterprise, Cray Inc., Intel Corporation and Open-Silicon. With a robust skill set that includes Floorplanning, Communications, Debugging, Functional Verification, RTL design and more. John Sizer has 3 emails and 2 mobile phone numbers on RocketReach.
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