John Sizer Email & Phone Number
Physical Design Manager @ Hewlett Packard Enterprise
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John Sizer Location
- Eau Claire, WI, US
John Sizer Work
- Physical Design Manager @ (January 2020 - Present)
- Master Technologist @ (January 2020 - Present)
- Senior Physical Design Engineer @ (February 2019 - January 2020)
- Sr Design Engineer @ (May 2013 - February 2019)
- Sr. Engineer @ Open-Silicon (December 2009 - April 2013)
- Sr. Engineer @ (July 1997 - December 2009)
- Design Verification Engineer @ (January 1993 - January 1997)
- Technical Lead - Systems Test @ (January 1988 - January 1993)
John Sizer Skills
- Floorplanning
- Communications
- Debugging
- Functional Verification
- RTL design
- Intel
- ASIC
- Verilog
- Formal Verification
- TCL
- SoC
- EDA
- Primetime
- Timing Closure
- SystemVerilog
- Semiconductors
- Physical Design
- Design
- Static Timing Analysis
- Clock Tree Synthesis
- IC
John Sizer Summary
- John Sizer, based in Eau Claire, WI, US, is currently a Physical Design Manager at Hewlett Packard Enterprise. John Sizer brings experience from previous roles at Hewlett Packard Enterprise, Cray Inc., Intel Corporation and Open-Silicon. With a robust skill set that includes Floorplanning, Communications, Debugging, Functional Verification, RTL design and more. John Sizer has 3 emails and 2 mobile phone numbers on RocketReach.
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