John Shafran Email & Phone Number
Power System Architect @ Google
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John Shafran Location
- San Jose, CA, US
John Shafran Work
- Power System Architect @ (December 2019 - Present)
- Principal Analog Design Engineer @ (June 2018 - November 2019)
- Principal Analog Design Engineer @ (January 2018 - June 2018)
- Principal Analog Design Engineer @ (April 2016 - December 2017)
- Staff Analog Design Engineer @ (June 2015 - March 2016)
- Senior Analog Design Engineer @ (March 2012 - June 2015)
- Senior IC Design Engineer @ (September 2008 - March 2012)
- Senior IC Design Engineer and IC Design Engineer @ (July 2005 - September 2008)
- Graduate Researcher @ (June 2004 - June 2005)
John Shafran Education
- Massachusetts Institute of Technology
Bachelor of Science (Electrical Science and Engineering)
2000-2005 - Massachusetts Institute of Technology
Masters of Engineering (Electrical Engineering and Computer Science)
2000-2005
John Shafran Skills
- ASIC
- Analog
- Analog Circuit Design
- Analog Design
- CMOS
- Cadence
- Cadence Skill
- Cadence Virtuoso
- Circuit Design
- Circuits
- Data Conversion
- Debugging
- Integrated Circuit Design
- LED lighting systems
- Low-power Design
- Matlab
- Mixed Signal
- Mixed-Signal IC Design
- Power Electronics
- Power Management
- Semiconductors
- Team Leadership
- Verilog-A
- Voltage References
John Shafran Summary
- John Shafran, based in San Jose, CA, US, is currently a Power System Architect at Google. John Shafran brings experience from previous roles at Renesas Electronics and Intersil (acquired by Renesas). John Shafran holds a 2000 - 2005 Bachelor of Science in Electrical Science and Engineering @ Massachusetts Institute of Technology. With a robust skill set that includes ASIC, Analog, Analog Circuit Design, Analog Design, CMOS and more. John Shafran has 5 emails and 1 mobile phone numbers on RocketReach.
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