John Garro Email & Phone Number
Manager, Electrical Engineering - Digital, FPGA, and Embedded Design @ Vertex Aerospace
5 free lookup(s).
John Garro Location
- Indianapolis, IN, US
John Garro Work
- 2021 - now Manager, Electrical Engineering - Digital, FPGA, and Embedded Design @
- 2021 - 2021 Electrical Engineering Manager @
- 2019 - 2021 Principal Electrical Engineer @ Raytheon Intelligence, Information, and Services
- 2014 - 2019 Senior Electrical Engineer II @ Raytheon Intelligence, Information and Services
- 2009 - 2014 Senior Electrical Engineer I @ Raytheon Intelligence, Information, and Services
- 2008 - 2008 Electrical Engineer Summer Intern @
John Garro Education
- University of Notre Dame 2005 - 2009
John Garro Skills
- Digital Circuit Design
- Altera Quartus
- VHDL
- ModelSim
- Altium Designer
- Matlab
- Electronics Hardware Design
- Altera Qsys
- Lattice Diamond
- Logic Analyzer
- Oscilloscope
- Microsemi Libero
- FPGA Design
- UART
- USB
- SPI
- I2C
- Ethernet
- 1553
- PCI
- PCIe
- RS232
- Mathematica
- RS422
- LVDS
- SATA
- RS170
- DisplayPort
- MIL-STD-810
- MIL-STD-704
- VGA
- MIL-STD-461
- MIL-STD-1275
- Microsoft Excel
- Microsoft Powerpoint
- Microsoft Visio
- Microsoft Word
- FPGA
- System Architecture
- Mil Std 461
- Mil Std 810
- Mil Std 704
- Mil Std 1275
John Garro Summary
- John Garro, based in Indianapolis, IN, US, is currently a Manager, Electrical Engineering - Digital, FPGA, and Embedded Design at The Vertex Company. John Garro brings experience from previous roles at Raytheon Intelligence & Space, Raytheon Intelligence, Information, and Services and Raytheon Intelligence, Information and Services. John Garro holds a 2005 - 2009 University of Notre Dame. With a robust skill set that includes Digital Circuit Design, Altera Quartus, VHDL, ModelSim, Altium Designer and more. John Garro has 2 emails and 1 mobile phone numbers on RocketReach.
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