John Factoran Email & Phone Number
Sr. Staff ASIC Design Engineer @ Northrop Grumman
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John Factoran Location
- United States
John Factoran Work
- Sr. Staff ASIC Design Engineer @ (November 2023 - Present)
- Senior Staff Engineer @ (October 2012 - October 2023)
- Senior ASIC Engineer @ (February 2010 - October 2012)
- Staff ASIC Design Engineer @ (February 2009 - February 2010)
- Staff ASIC Design Engineer @ (December 2000 - February 2010)
- ASIC Design Engineer @ Mykotronx (May 1996 - December 2000)
John Factoran Education
- Loyola Marymount University
Master of Science
1997-2000 - Loyola Marymount University
Bachelor of Science
1991-1995 - St. John Bosco
High School
1987-1991
John Factoran Skills
- AMBA AHB
- SoC
- ASIC
- RTL design
- Verilog
- FPGA
- Functional Verification
- ModelSim
- VHDL
- Digital Design
- TCL
- Xilinx
- Perl
- Debugging
- Primetime
- Semiconductors
- Static Timing Analysis
- Embedded Systems
- Simulation
- RTL coding
- DFT
- Shell Scripting
- IP
- ARM
- Architecture
- Formal Verification
- IC
- Firmware
- SystemVerilog
- Integrated Circuit Design
- System on a Chip (SoC)
- Application-Specific Integrated Circuits (ASIC)
- ARM Architecture
- Field-Programmable Gate Arrays (FPGA)
- Integrated Circuits (IC)
John Factoran Summary
- John Factoran, based in United States, is currently a Sr. Staff ASIC Design Engineer at Northrop Grumman. John Factoran brings experience from previous roles at Qualcomm, SafeNet, CSR and SiRF Technology. John Factoran holds a 1997 - 2000 Master of Science @ Loyola Marymount University. With a robust skill set that includes AMBA AHB, SoC, ASIC, RTL design, Verilog and more. John Factoran has 1 emails and 1 mobile phone numbers on RocketReach.
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