John Digeronimo Email
Information Service Specialist Staff @ ASRC Federal
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John Digeronimo Location
- Belle Haven, VA, US
John Digeronimo Work
- Information Service Specialist Staff @ (September 2014 - Present)
- Patent Examiner - Electrical Engineering @ United States Patent and Trademark Office (USPTO) (September 2013 - August 2014)
- Principal Design Engineer @ Standard Microsystems Corporation (SMSC) (December 1982 - March 2010)
- Engineering Intern @ (May 1981 - January 1982)
- MOS Design Engineer @ Texas Instruments (January 1982 - January 1982)
- Engineering Intern @ (May 1979 - August 1980)
John Digeronimo Education
- Stony Brook University
MSEE (Electrical Engineering)
1983-1987 - Bradley University
BSEE (Electrical Engineering)
1978-1982
John Digeronimo Skills
- BIST
- Logic Design
- Cadence Virtuoso
- Linux
- C
- Awk
- Perl
- Lotus Notes
- Vi
- Memory Design
- RTL design
- Processors
- ASIC
- Digital Design
- CAD
- Integrated Circuit Design
- TCL
- Circuit Design
- Bugzilla
- Semiconductor Design
- Microsoft Office
- Mixed Signal
- CMOS
- LVS
- Sun Grid Engine
- Unix Administration
- FPGA
- SoC
- Perforce
- Electrical Engineering
- Unix Shell Scripting
- EDA
- Primetime
- Solaris
- Csh
- Sed
- DRC
- Semiconductors
- Physical Design
- SunOS
- Lsf
- Unix
- Shell Scripting
John Digeronimo Summary
- John Digeronimo, based in Belle Haven, VA, US, is currently a Information Service Specialist Staff at ASRC Federal. John Digeronimo brings experience from previous roles at United States Patent and Trademark Office (USPTO), Standard Microsystems Corporation (SMSC), Transcontrol and Texas Instruments. John Digeronimo holds a 1983 - 1987 MSEE in Electrical Engineering @ Stony Brook University. With a robust skill set that includes BIST, Logic Design, Cadence Virtuoso, Linux, C and more. John Digeronimo has 2 emails on RocketReach.
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