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John Ayers Location
Portland, OR, US
John Ayers Work
2026 -now Principal Engineer @
2025 -2026 Principal Engineer @
2014 -2024 Principal Engineer and Manager, System on a Chip Architecture, Datacenter and High-Performance Group @
2011 -2014 Fabric Architecture and Design @
2008 -2010 Engineering Manager @
2004 -2008 Senior Design Engineer @
2003 -2004 Engineering Manager @
1998 -2002 Design Engineer @
1996 -1998 Design Engineer @
John Ayers Education
Stanford University
MSEE (Computer Engineering)
1996-2001
University of Washington
BSEE (Computer Engineering)
1992-1996
John Ayers Skills
Computer Architecture
Processors
SoC
Microarchitecture
Debugging
ASIC
VLSI
Microprocessors
CMOS
Physical Design
Static Timing Analysis
IC
SystemVerilog
Circuit Design
Perl
Programming
EDA
Computer Engineering
High Performance Computing
Design Automation
Mixed Signal
Product Management
Circuit Layout
Team Management
X86
Hardware Design
Performance Analysis
x86 Assembly
Design Verification
Many Integrated Cores
Integrated Design
High Performance Interconnects
Signal Integrity
Signal Processing
Reliability Accessibility Serviceability
Design for Testability
Design For Debug
Design for Manufacturing
Design For Reuse
Design For Validation
Product Development
Process Engineering
Design Methodology
Low Power Design
Technical Documentation
Hardware Architecture
Low-power Design
Graphic Design
Engineering
Intel
Customer Service
Project Planning
John Ayers Summary
John Ayers, based in Portland, OR, US, is currently a Principal Engineer at MediaTek. John Ayers brings experience from previous roles at Parade Technologies, Inc. and Intel Corporation. John Ayers holds a 1996 - 2001 MSEE in Computer Engineering @ Stanford University. With a robust skill set that includes Computer Architecture, Processors, SoC, Microarchitecture, Debugging and more. John Ayers has 2 emails and 1 mobile phone numbers on RocketReach.
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