Joao Lacerda Email & Phone Number

Joao Lacerda Email & Phone Number

MTS and ASIC LAYOUT ENGINEER @ AMD

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Joao Lacerda's Location

Orlando, Florida, United States

Joao Lacerda's Work

  • Logic Design and Verification Engineer @ Philips (Now NXP) Semiconductors & TriMedia Technologies
  • Component Design Engineer @ Intel Corporation

Joao Lacerda's Education

  • University of California, Irvine

    Master of Science (MS) (Electrical and Computer Engineering)

Joao Lacerda's Skills

  • P&R
  • Milestones
  • Hardware Architecture
  • Logic Design
  • Specifications
  • Computer Architecture
  • Floorplanning
  • Code
  • Algorithms
  • C

Joao Lacerda's Summary

Joao Lacerda, based in Orlando, Florida, United States, is currently a MTS and ASIC LAYOUT ENGINEER at AMD, bringing experience from previous roles at Ambiq Micro, Freescale Semiconductor, Philips (Now NXP) Semiconductors & TriMedia Technologies and Intel Corporation. Joao Lacerda holds a Master of Science (MS) in Electrical and Computer Engineering @ University of California, Irvine. With a robust skill set that includes P&R, Milestones, Hardware Architecture, Logic Design, Specifications and more, Joao Lacerda contributes valuable insights to the industry. Joao Lacerda has 4 emails and 1 mobile phone number on RocketReach.

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