Jitendra Shaw Email
SOC design verification Engineer @ Intel Corporation
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Jitendra Shaw Location
- Bengaluru, KA, IN
Jitendra Shaw Work
- SOC design verification Engineer @ (May 2024 - Present)
- Senior Design Verification Engineer @ (September 2023 - April 2024)
- SOC design Verification Engineer @ (December 2020 - August 2023)
- Member Of Technical Staff @ (July 2017 - November 2020)
- Senior Design Engineer @ (December 2013 - June 2017)
- Lead Design Engineer at Freescale Semiconductor @ (May 2008 - November 2013)
- Design Engineer @ (October 2007 - April 2008)
- design engineer @ (July 2005 - September 2007)
Jitendra Shaw Education
- Jadavpur University
Bachelor of Engineering (BE) (Electronics and Communications Engineering)
2001-2005 - T.D.B college 1998-2000
Jitendra Shaw Skills
- ASIC
- AXI
- Application-Specific Integrated Circuits (ASIC)
- CXL
- Cache Coherency
- DDR
- DDR2
- EDA
- Formal Verification
- Functional Verification
- Gate Level Simulation
- Low power verification
- Power Management
- RTL Verification
- Semiconductors
- Simulations
- SoC
- Specman
- System on a Chip (SoC)
- SystemVerilog
- UPF
- Universal Verification Methodology (UVM)
- VLSI
- Verilog
- JTAG
- Design
Jitendra Shaw Summary
- Jitendra Shaw, based in Bengaluru, KA, IN, is currently a SOC design verification Engineer at Intel Corporation. Jitendra Shaw brings experience from previous roles at Tessolve Semiconductor Pvt. Ltd., Intel Corporation and AMD. Jitendra Shaw holds a 2001 - 2005 Bachelor of Engineering (BE) in Electronics and Communications Engineering @ Jadavpur University. With a robust skill set that includes ASIC, AXI, Application-Specific Integrated Circuits (ASIC), CXL, Cache Coherency and more. Jitendra Shaw has 4 emails on RocketReach.
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