Jinjin He Email & Phone Number
ASIC Design Engineer @ Meta
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Jinjin He Location
- Sunnyvale, CA, US
Jinjin He Work
- 2024 -now ASIC Design Engineer @
- 2020 -2024 Senior Design Manager @
- 2019 -2020 Design Manager @
- 2016 -2019 Senior Staff Engineer @
- 2014 -2016 Staff Design Engineer @
- 2010 -2014 Senior Design Engineer @
- 2006 -2010 Research Assistant @
- 2005 -2006 Design Engineer @ Accel Semi. Co, Shanghia, China
- 2003 -2006 Research assistant @
Jinjin He Education
- Oregon State University
Ph. D. (VLSI architecture design for DSP and communication system)
2006-2010 - Fudan University
Master (Electrical Engineering)
2003-2006 - Fudan University
B.S. (Electrical Engineering)
1999-2003
Jinjin He Skills
- Digital Signal Processors
- Computer Architecture
- RTL design
- Digital Communication
- CMOS
- ModelSim
- VLSI
- Algorithms
- Electrical Engineering
- Xilinx
- Digital Signal Processing
- IC
- FPGA
- Verilog
- Circuit Design
- ASIC
- Digital Signal
Jinjin He Summary
- Jinjin He, based in Sunnyvale, CA, US, is currently a ASIC Design Engineer at Meta. Jinjin He brings experience from previous roles at ScaleFlux and Marvell Semiconductor. Jinjin He holds a 2006 - 2010 Ph. D. in VLSI architecture design for DSP and communication system @ Oregon State University. With a robust skill set that includes Digital Signal Processors, Computer Architecture, RTL design, Digital Communication, CMOS and more. Jinjin He has 4 emails and 1 mobile phone numbers on RocketReach.
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