verification, using verilog, system verilog and assertions.
RTL lint checking
formal equivalence check using formality or conformal
Static Timing Analysis
Logic Synthesis
DFT
Using
Design
Using Verilog
System Verilog And Assertions
Formal Equivalence
SoC
Verification
Jinguo Gu Summary
Jinguo Gu, based in United States, is currently a SoC Design Engineer at Altera. Jinguo Gu brings experience from previous roles at Intel Corporation, Renesas Electronics Corporation, WiQuest Communications and Texas Instruments. Jinguo Gu holds a North Carolina State University. With a robust skill set that includes ASIC design, verification, using verilog, system verilog and assertions., RTL lint checking, formal equivalence check using formality or conformal, Static Timing Analysis and more. Jinguo Gu has 2 emails and 1 mobile phone numbers on RocketReach.
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