Jing Bai Email & Phone Number
Principal Physical Design Engineer @ Marvell India
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Jing Bai Location
- California, United States
Jing Bai Work
- Principal Physical Design Engineer @ (April 2019 - Present)
- Physical Design Engineer @ (January 2017 - March 2019)
- Senior Staff Physical Design Engineer @ (February 2012 - December 2016)
- Logic CAD Engineer II @ (January 2011 - February 2012)
- ASIC design engineer intern @ (June 2009 - August 2009)
Jing Bai Education
- University of Southern California
MS (Electrical Engineering)
2008-2010 - Beijing University of Technology
B.E (Electrical Science and Technology)
Jing Bai Skills
- ASIC
- Verilog
- Static Timing Analysis
- VLSI
- TCL
- Physical Design
- ModelSim
- VHDL
- DRC
- LVS
- Integrated Circuit Design
- Logic Synthesis
- NCSim
- Circuit Design
- SPICE
- Perl
- Application-Specific Integrated Circuits (ASIC)
- Very-Large-Scale Integration (VLSI)
- Planning
- Power
- Physical Verification
- Application Specific Integrated Circuits Asic
- Analytical Skill
- Design
- Very Large Scale Integration Vlsi
- Power Analysis
- Analysis
- Verification
- Application Specific Integrated Circuits
- Very Large Scale Integration
Jing Bai Summary
- Jing Bai, based in California, United States, is currently a Principal Physical Design Engineer at Marvell Semiconductor. Jing Bai brings experience from previous roles at Intel Corporation, Broadcom, NetLogic Microsystems and Semiconductor Manufacturing International Corporation (SMIC). Jing Bai holds a 2008 - 2010 MS in Electrical Engineering @ University of Southern California. With a robust skill set that includes ASIC, Verilog, Static Timing Analysis, VLSI, TCL and more. Jing Bai has 2 emails and 3 mobile phone numbers on RocketReach.
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