Jin Han Email & Phone Number

Jin Han Skills

• ASIC/SoC/FPGA front-end & back-end design
• • RTL coding and synthesis: Verilog, SystemVerilog, VHDL, Synopsys Design Compil
• • DFT: Synopsys DFT Compiler, LogicVision
• • Static timing analysis: Primetime
• • Verification and debugging: Modelsim, Verdi, NCSIM, VCS, Specman
• • Formal verification: LEC, Formality
• • Planning and managing SoC/ASIC layout
• • Low-power design techniques: UPF flow, MVRC
• Static Timing Analysis
• SoC
• ASIC
• Verilog
• FPGA
• Logic Synthesis
• RTL design
• ModelSim
• Functional Verification
• Integrated Circuit Design
• C
• Hardware
• Electronics
• Debugging
• Hardware Architecture
• EDA
• SystemVerilog
• VLSI
• USB
• Application-Specific Integrated Circuits (ASIC)
• CMOS
• TCL
• IC
• Field-Programmable Gate Arrays (FPGA)
• System on a Chip (SoC)
• Field Programmable Gate Arrays Fpga
• Specman
• System On A Chip Soc
• Rtl Coding And Synthesis
• Low Power Design Techniques
• DFT
• Verification And Debugging
• Formal Verification
• NCSim
• Logicvision
• Synopsys Design Compil
• Formality
• Application Specific Integrated Circuits Asic
• Lec
• Upf Flow
• VHDL
• VCS
• Planning And Managing Soc/Asic Layout
• Primetime
• Synopsys Dft Compiler
• Mvrc
• Asic/Soc/Fpga Front End And Back End Design
• Verdi
• Application Specific Integrated Circuits
• Field Programmable Gate Arrays
• System on a Chip