Senior Member of Technical Staff @ (January 2025 - April 2026)
Sr Verification Project Lead @ (April 2016 - March 2025)
Sr. Design Verification Engineer @ (April 2013 - April 2016)
Sr Verification Engineer @ (August 2011 - March 2013)
Sr. ASIC Engineer @ (April 2011 - August 2011)
ASIC Engineer @ (October 2007 - March 2011)
SOC Verification Engineer(Contractor) @ (September 2010 - December 2010)
R and D Engineer @ M/S VAMENDU (June 2006 - October 2007)
Jigneshkumar Patel Education
Sardar Patel University
B.E (Electronics & Communication)
2003-2006
Government Polytechanic, Gandhinagar
Diploma (Electronics & Communication)
2000-2003
Jigneshkumar Patel Skills
Open Verification
Computer Architecture
C
Debugging
System On A Chip Soc
Functional Verification
Perl
RTL design
UVM
ASIC
VMM
VLSI
Verilog
Microcontrollers
NCSim
Xilinx
TCL
Microchip
Embedded Systems
Veritas Cluster Server
Application Specific Integrated Circuits Asic
FPGA
RTL coding
Open Verification Methodology
SoC
VHDL
ModelSim
Timing Closure
SystemVerilog
Design Automation
Simulations
Physical Design
Semiconductors
Design
Static Timing Analysis
Digital Signal Processors
Digital Signal
Very Large Scale Integration Vlsi
Hardware
Automation
Application Specific Integrated Circuits
System on a Chip
Very Large Scale Integration
Jigneshkumar Patel Summary
Jigneshkumar Patel, based in Folsom, CA, US, is currently a Manager Silicon Design Engineering at AMD. Jigneshkumar Patel brings experience from previous roles at AMD, Intel Corporation, Synapse Design Automation Inc. and IBM. Jigneshkumar Patel holds a 2003 - 2006 B.E in Electronics & Communication @ Sardar Patel University. With a robust skill set that includes Open Verification, Computer Architecture, C, Debugging, System On A Chip Soc and more. Jigneshkumar Patel has 2 emails and 2 mobile phone numbers on RocketReach.
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