Jigneshkumar Patel Location
- Folsom, CA, US
Jigneshkumar Patel Work
- 2025 - now Senior Member of Technical Staff @
- 2016 - 2025 Sr Verification Project Lead @
- 2013 - 2016 Sr. Design Verification Engineer @
- 2011 - 2013 Sr Verification Engineer @
- 2011 - 2011 Sr. ASIC Engineer @
- 2007 - 2011 ASIC Engineer @
- 2010 - 2010 SOC Verification Engineer(Contractor) @
- 2006 - 2007 R and D Engineer @ M/S VAMENDU
Jigneshkumar Patel Education
- Sardar Patel University
B.E (Electronics & Communication)
2003 - 2006 - Government Polytechanic, Gandhinagar
Diploma (Electronics & Communication)
2000 - 2003
Jigneshkumar Patel Skills
- Open Verification
- Computer Architecture
- C
- Debugging
- System On A Chip Soc
- Functional Verification
- Perl
- RTL design
- UVM
- ASIC
- VMM
- VLSI
- Verilog
- Microcontrollers
- NCSim
- Xilinx
- TCL
- Microchip
- Embedded Systems
- Veritas Cluster Server
- Application Specific Integrated Circuits Asic
- FPGA
- RTL coding
- Open Verification Methodology
- SoC
- VHDL
- ModelSim
- Timing Closure
- SystemVerilog
- Design Automation
- Simulations
- Physical Design
- Semiconductors
- Design
- Static Timing Analysis
- Digital Signal Processors
- Digital Signal
- Very Large Scale Integration Vlsi
- Hardware
- Automation
- Application Specific Integrated Circuits
- System on a Chip
- Very Large Scale Integration
Jigneshkumar Patel Summary
- Jigneshkumar Patel, based in Folsom, CA, US, is currently a Senior Member of Technical Staff at AMD. Jigneshkumar Patel brings experience from previous roles at Intel Corporation, Synapse Design Automation Inc., IBM and eInfochips. Jigneshkumar Patel holds a 2003 - 2006 B.E in Electronics & Communication @ Sardar Patel University. With a robust skill set that includes Open Verification, Computer Architecture, C, Debugging, System On A Chip Soc and more. Jigneshkumar Patel has 2 emails and 2 mobile phone numbers on RocketReach.
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