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Jigar Patel Location
Leicester, GB
Jigar Patel Work
FPGA Design Engineer @ (June 2024 - Present)
Senior FPGA Design Engineer @ (June 2011 - June 2024)
Senior Embedded Systems Engineer @ RFTechnics Ltd (September 2009 - June 2011)
FPGA Engineer @ ATE Communications (September 2004 - April 2009)
Jigar Patel Education
University of Southern Queensland
Master of Business Administration - MBA (Project Management)
2004-2008
Ryerson University
Bachelor's degree (Electrical and Electronics Engineering)
2000-2004
Jigar Patel Skills
Analog Signal Processing
Application-Specific Integrated Circuits (ASIC)
Block Diagrams
C (Programming Language)
Clock domain crossing
Communication
Creativity Skills
DAC
Debuggers
Digital Logic
Digital Signal Processing
Dsp
Electronics
Embedded Linux
Engineering
English
FPGA
Field-Programmable Gate Arrays (FPGA)
Floorplanning
Frequency Analysis
Hardware Verification
Intel Quartus Prime
Leadership
Management
Microchip Libero
Microprocessors
Microsoft Office
ModelSim
Operating Systems
PCB design
Printed Circuit Board (PCB) Design
Problem Solving
Product Requirements
Project Management
Python (Programming Language)
Resource Allocation
Static Timing Analysis
SystemVerilog
Systems Design
TI DSPs
Team Leadership
Teamwork
Timing
Timing Closure
VHDL
Xilinx ISE
adc
asic
vb6
zilog
Jigar Patel Summary
Jigar Patel, based in Leicester, GB, is currently a FPGA Design Engineer at Guidance Marine. Jigar Patel brings experience from previous roles at Newtons4th Ltd, RFTechnics Ltd and ATE Communications. Jigar Patel holds a 2004 - 2008 Master of Business Administration - MBA in Project Management @ University of Southern Queensland. With a robust skill set that includes Analog Signal Processing, Application-Specific Integrated Circuits (ASIC), Block Diagrams, C (Programming Language), Clock domain crossing and more. Jigar Patel has 1 emails on RocketReach.
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