Jie Ding Email & Phone Number
Senior Principal @ Ayar Labs
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Jie Ding Location
- Santa Clara, CA, US
Jie Ding Work
- 2020 -now Senior Principal @
- 2015 -2020 Principal Verification Engineer @
- 2012 -2015 Senior Staff Verificaton Engineer @
- 2011 -2012 Senior Staff Verification Engineer @
- 2008 -2011 Senior Verification Engineer @
- 2005 -2008 Senior Verification Engineer @
- 2000 -2005 Senior verification Engineer @
Jie Ding Education
- Duke University
MS (Electrical/Computer Engineering)
1998-2000 - Southeast University
MS (Electrical Engineering)
1995-1998 - University of Electronic Science and Technology of China
Bachelor of Science (BS) (Electrical and Electronics Engineering)
1991-1995
Jie Ding Skills
- SERDES
- SystemVerilog
- SoC
- ASIC
- Verilog
- FPGA
- RTL design
- Debugging
- IC
- EDA
- Semiconductors
- Digital Signal Processors
- TCL
- Functional Verification
- Perl
- Embedded Systems
- Mixed Signal
- Firmware
- ModelSim
- Static Timing Analysis
- PCIe
- Matlab
Jie Ding Summary
- Jie Ding, based in Santa Clara, CA, US, is currently a Senior Principal at Ayar Labs. Jie Ding brings experience from previous roles at Innovium Inc., Qualcomm, Xilinx and Amlogic Inc.. Jie Ding holds a 1998 - 2000 MS in Electrical/Computer Engineering @ Duke University. With a robust skill set that includes SERDES, SystemVerilog, SoC, ASIC, Verilog and more. Jie Ding has 2 emails and 1 mobile phone numbers on RocketReach.
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