Jianping Wen Email & Phone Number
Principal Design Engineer @ Cirrus Logic
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Jianping Wen Location
- Austin, TX, US
Jianping Wen Work
- Principal Design Engineer @ (November 2017 - Present)
- Senior Analog and Mixed Signal IC Designer and Project Leader @ (August 2010 - November 2017)
- Senior Analog and Mixed Signal IC Design Engineer @ (August 2008 - August 2010)
- Analog and Mixd Signal IC Design Engineer @ (November 2004 - August 2008)
- Analog and Mixed Signal IC design @ (January 2001 - January 2004)
- Analog and Mixed Signal IC designer @ (January 2000 - January 2001)
Jianping Wen Education
- Oregon State University
E
1998-2000 - Penn State University
IME
1996-1998 - Nanjing University
Physics
1982-1989
Jianping Wen Skills
- ASIC
- Analog
- Analog Circuit Design
- CMOS
- Circuit Design
- Embedded Systems
- IC
- Integrated Circuit Design
- Integrated Circuits (IC)
- Mixed Signal
- PLL
- Signal Integrity
- Signal Processing
Jianping Wen Summary
- Jianping Wen, based in Austin, TX, US, is currently a Principal Design Engineer at Cirrus Logic. Jianping Wen brings experience from previous roles at Avnera Corporation, Synopsys Inc and Lattice Semiconductor. Jianping Wen holds a 1998 - 2000 E @ Oregon State University. With a robust skill set that includes ASIC, Analog, Analog Circuit Design, CMOS, Circuit Design and more. Jianping Wen has 3 emails and 1 mobile phone numbers on RocketReach.
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