Jianjun Yu's Location
Shanghai, China
Jianjun Yu's Work
- R and D Engineer @ Synopsys Inc
- ASIC Design Engineer @ Hisilicon
- ASIC Customer Design Intern @ LSI, an Avago Technologies Company
Jianjun Yu's Education
- Fudan University
ME, Digital VLSI, Microelectronic. Department
2010 - 2012 - Huazhong University of Science and Technology
BE, Electronic Sci.&Tech. Department
2005 - 2009
Jianjun Yu's Skills
- SoC
- ASIC
- Verilog
- Static Timing Analysis
- RTL design
Jianjun Yu's Summary
Jianjun Yu, based in Shanghai, China, is currently a R and D Engineer at Synopsys, bringing experience from previous roles at Hisilicon and LSI Corporation. Jianjun Yu holds a 2010 - 2012 ME, Digital VLSI, Microelectronic. Department @ Fudan University. With a robust skill set that includes SoC, ASIC, Verilog, Static Timing Analysis, RTL design and more, Jianjun Yu contributes valuable insights to the industry. Jianjun Yu has 1 email on RocketReach.
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