Jeffrey Low Email
FPGA Engineer @ DSO National Laboratories
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Jeffrey Low Location
- Singapore
Jeffrey Low Work
- Member Of Technical Staff @ (June 2021 - Present)
- FPGA Engineer @ (June 2021 - Present)
- Research Intern @ (May 2024 - August 2024)
- Research Intern @ (June 2020 - May 2021)
- Research Intern @ (May 2019 - August 2019)
- Research Intern @ (March 2018 - July 2018)
- Admin Support Assistant @ (February 2016 - February 2018)
- Research Intern @ (September 2015 - January 2016)
- Research Intern @ (May 2015 - September 2015)
- Research Intern @ (February 2015 - April 2015)
Jeffrey Low Education
- Carnegie Mellon University
Master of Science - MS (Electrical and Computer Engineering)
2023-2025 - National University of Singapore
Bachelor of Engineering - BE (Electrical and Electronics Engineering)
2018-2021 - Linköping University 2019-2019
Jeffrey Low Summary
- Jeffrey Low, based in Singapore, is currently a FPGA Engineer at DSO National Laboratories. Jeffrey Low brings experience from previous roles at DSO National Laboratories and AMD. Jeffrey Low holds a 2023 - 2025 Master of Science - MS in Electrical and Computer Engineering @ Carnegie Mellon University. Jeffrey Low has 2 emails on RocketReach.
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