Jeff Shaffer Email & Phone Number
FPGA Verification and Validation Engineer @ NASA Jet Propulsion Laboratory (Raytheon / Correct Designs)
Jeff Shaffer's Location
Westminster, MD, US
Jeff Shaffer's Work
- FPGA Verification and Validation Engineer @ NASA Jet Propulsion Laboratory (Raytheon / Correct Designs)
- Owner, Manager and Individual Contributor @ Mutt Logic, LLC
- Senior ASIC Verification Engineer @ Viasat / Effect Photonics (Correct Designs)
- Senior ASIC Verification Engineer @ IBM Research (Collins Consulting)
- Senior Software Engineer @ Survae
- Engineer and Manager @ Hewlett Packard Enterprise
- Engineer @ Supercomputer Systems Incorporated
- Project Design Engineer @ Megatek
- Project Test Engineer @ Wavetek
- Test Engineer @ DatagraphiX
Jeff Shaffer's Education
- The Johns Hopkins University
Master of Science (Computer Science)
2000 - 2003 - DeVry University
(Electrical Engineering)
1982 - 1984
Jeff Shaffer's Skills
- Embedded Software
- Linux
- C
- Computer Hardware
- Debugging
- System on a Chip Soc
- Perl
- Functional Verification
- Microprocessors
- Processors
Jeff Shaffer's Summary
Jeff Shaffer, based in Westminster, MD, US, is currently a FPGA Verification and Validation Engineer at NASA Jet Propulsion Laboratory (Raytheon / Correct Designs), bringing experience from previous roles at Mutt Logic, LLC, Viasat / Effect Photonics (Correct Designs), IBM Research (Collins Consulting) and Survae. Jeff Shaffer holds a 2000 - 2003 Master of Science in Computer Science @ The Johns Hopkins University. With a robust skill set that includes Embedded Software, Linux, C, Computer Hardware, Debugging and more, Jeff Shaffer contributes valuable insights to the industry. Jeff Shaffer has 2 emails on RocketReach.
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