Principal Consultant @ Ebert Embedded (February 2017 - February 2019)
Sr. Director and Sr. Principal Engineer, ASICs and Hardware @ (March 2015 - January 2017)
Director, ASIC Engineering @ (August 2012 - February 2015)
ASIC Design Manager @ (August 2010 - July 2012)
Technical Leader @ (April 2007 - July 2010)
Senior Staff Engineer @ (May 2005 - April 2007)
Principal Engineer @ (January 2005 - May 2005)
Lead Verification Engineer @ (August 1998 - December 2004)
Member of the Technical Staff @ (September 1994 - August 1998)
Jeff Ebert Education
University of Virginia
MS
1993-1994
University of Virginia
BS
1989-1992
Jeff Ebert Skills
ASIC
Application-Specific Integrated Circuits (ASIC)
EDA
Embedded Systems
FPGA
Field-Programmable Gate Arrays (FPGA)
Functional Verification
Hardware Architecture
IC
Integrated Circuit Design
Microprocessors
Processors
RTL Design
Semiconductors
SoC
System Architecture
System Design
SystemC
SystemVerilog
TCL
UVM
VLSI
Verilog
Field Programmable Gate Arrays Fpga
Application Specific Integrated Circuits Asic
Verification
Application Specific Integrated Circuits
Field Programmable Gate Arrays
Jeff Ebert Summary
Jeff Ebert, based in Half Moon Bay, CA, US, is currently a Senior Manager, IO, Embedded, and Debug Software at Cerebras Systems. Jeff Ebert brings experience from previous roles at Ebert Embedded and Silver Spring Networks. Jeff Ebert holds a 1993 - 1994 MS @ University of Virginia. With a robust skill set that includes ASIC, Application-Specific Integrated Circuits (ASIC), EDA, Embedded Systems, FPGA and more. Jeff Ebert has 1 emails and 1 mobile phone numbers on RocketReach.
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