Jeevan Mathew Email & Phone Number
Strategic Sales Leadership @ LanceSoft Europe
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Jeevan Mathew Location
- North Brabant, Netherlands
Jeevan Mathew Work
- Strategic Sales Leadership @ (August 2026 - Present)
- Director Sales @ (April 2025 - June 2026)
- Chief Executive Officer @ (December 2019 - March 2025)
- Co-Founder @ (September 2020 - January 2025)
- Director Sales @ (April 2018 - December 2019)
- Advanced Solutions Manager @ (September 2016 - April 2018)
- Business Development Manager @ (September 2014 - August 2016)
- C.O.E Head @ (October 2012 - September 2014)
- Technical Manager @ (September 2010 - October 2012)
- Design Engineer @ (July 2007 - September 2010)
- Design Engineer @ Texas Instruments (March 2005 - March 2007)
- Member technical staff @ (January 2003 - January 2005)
Jeevan Mathew Education
- cdac
Diploma in VLSI Design (VLSI)
2002-2003 - PSNA CET
Bachelor of Engineering (B.E.) (Electrical, Electronics and Communications Engineering)
1998-2002 - Bhavans adarsha vidyalaya
12th CBSE (Physics,chemisty,Maths and Computing)
1996-1998 - toc-h school
10th Grade CBSE (Science)
1984-1995 - PSNA
Bachelor of Engineering (B.E.) (Electrical, Electronics and Communications Engineering)
Jeevan Mathew Skills
- ARM
- ASIC
- Application-Specific Integrated Circuits (ASIC)
- C
- C++
- Debugging
- Device Drivers
- EDA
- Embedded Software
- Embedded Systems
- Exalens
- FPGA
- Field-Programmable Gate Arrays (FPGA)
- Functional Verification
- Microprocessors
- Mixed Signal
- ModelSim
- RTOS
- Semiconductors
- Simulations
- SoC
- System Design
- System on a Chip (SoC)
- TCL
- USB
- VHDL
- VLSI
- Verilog
- Very-Large-Scale Integration (VLSI)
- Illustrator
- Communications
- Photoshop
- Electronics
- Solutions
- Engineering
- Marketing
- Integration
- Schematic
- Writing
- Flexible
- Omni
- Certify
- Acts
- Compare
- Cards
- Memory
- Logic
- Channel
- Test Automation
- DDR3
- Field Programmable Gate Arrays Fpga
- Synplify
- Cookies
- Windows
- Perl
- Computing
- Cost
- Processors
- Juniper Technologies
- Mentoring
- Spi4.2
- Serving
- Data Mapping
- Failure
- Road
- Fire Management
- Third Party
- Detection
- Pins
- Pulse
- SPI
- Texas
- Management
- Contents
- Design
- PC
- Massive
- Digital Signal Processors
- Calls
- Route
- Sgmii
- Programming Languages
- TOC
- Checking
- PMC
- Modes
- Analyzer
- InDesign
- Silicon
- Bandwidth
- Debussy
- Routers
- CPLD
- Routing
- Gigabit
- Source
- Replacements
- Linux
- Ingress
- SRAM
- Human Resources
- Timely Delivery
- Chip Architecture
- Oscilloscope
- Qualification
- Linear
- Perl Script
- RTL design
- Networking
- Local Area Network
- Node
- Languages
- Customer Satisfaction
- System
- Telecommunications
- Timing
- Optical Fiber
- Education
- English
- Data Recovery
- Team Management
- Voice
- Tests
- Bangalore
- Radio Access Network
- Validation
- Reports
- From Scratch
- Strategy
- Xilinx
- Behavioral Modeling
- Internet Protocols
- Verifying
- Ethernet
- Asynchronous
- Testing
- Chips
- Serial
- Offshore
- Point to Point
- Circuit
- Point of Contact
- Cpci
- Modifying
- Bus
- Image
- Solution
- Scripting
- Hdlc
- Talk
- Venture Capital
- Leaves
- Analysis
- Hardware
- Written
- JTAG
- Mechanisms
- Switched
- Gates
- E3
- Constraints
- Systems Design
- E1
- Packet
- R
- Calling
- Power
- Blocks
- Test Planning
- Cyclone
- System on a Chip Soc
- Customer Interaction
- Composition
- Configurations
- Tamil
- FIX Protocol
- CCS
- Operating Systems
- The Environment
- Applications
- Interfacing
- Chinese
- Chassis
- Payment Industry
- Communication
- Negotiation
- IPS
- Reasonable
- Music
- Ring
- PLL
- Container
- Operations
- Values
- Suite
- Wipro
- Visibility
- Health Monitoring
- Ohio
- Maps
- PHY
- Dvt
- Checks
- Vera
- Partition
- RTL coding
- DSL
- Technical Discussions
- Project Planning
- Paths
- Code Composer Studio
- Altera
- Project
- Spec
- Supports
- Palladium
- Encapsulation
- Static Timing Analysis
- Multiplexes
- Mechanism
- WLAN
- Quartus
- Emulation
- Written Communication
- RS232
- Playing the Guitar
- Hex
- Logic Analyzer
- I2c
- Very Large Scale Integration Vlsi
- Presentations
- Board Level
- Sfp
- Nature
- Flash
- Responsibility
- Internal Audit
- DDR
- Badminton
- Boot
- Distribution
- Drop
- Studio
- Code
- Data Transfer
- Switch
- Malayalam
- Memories
- Logic Synthesis
- Interfaces
- Protocol Implementation
- Microsoft Exchange
- Reviews
- PCB design
- SDH
- Connectivity
- Lvds
- Forwards
- 4g
- Ports
- Regression Testing
- Logic Gates
- UART
- Dump
- Software
- Validating
- Cadence
- Mac
- Rings
- Sequence
- Kernel
- Ise
- Frame
- Requirement Specifications
- Sleep
- Test Cases
- India
- Application Specific Integrated Circuits Asic
- Rate
- Structural Engineering
- Network Communications
- MIPS
- Internal Controls
- IPC
- Veritas Cluster Server
- Interest Rates
- STM
- Telephony
- PDH
- Config
- Light
- Financial Transactions
- Switching
- Frames
- Conceptual Modeling
- Interventions
- Delivery
- Automatic
- Orcad
- Architecture
- Farms
- Chip
- Hindi
- Bridge
- Automation
- Srio
- Application Specific Integrated Circuits
- System on a Chip
- Very Large Scale Integration
- Field Programmable Gate Arrays
Jeevan Mathew Summary
- Jeevan Mathew, based in North Brabant, Netherlands, is currently a Strategic Sales Leadership at LanceSoft Europe. Jeevan Mathew brings experience from previous roles at ACL Digital, Bolgatty, Electricmile Pvt Ltd and Altran. Jeevan Mathew holds a 2002 - 2003 Diploma in VLSI Design in VLSI @ cdac. With a robust skill set that includes ARM, ASIC, Application-Specific Integrated Circuits (ASIC), C, C++ and more. Jeevan Mathew has 2 emails and 3 mobile phone numbers on RocketReach.
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