Senior Electronic Design Engineer @ (August 2021 - January 2023)
Research Assistant @ (February 2021 - August 2021)
Graduate Student @ (August 2018 - December 2020)
Jeevan Gowda Education
San José State University
Master's degree (Electrical and Electronics Engineering)
2018-2020
Visvesvaraya Technological University
Bachelor of Engineering - BE (Electrical, Electronics and Communications Engineering)
2013-2017
Jeevan Gowda Skills
Static Timing Analysis
RTL Design
Universal Verification Methodology (UVM)
Design
Debugging
Field-Programmable Gate Arrays (FPGA)
Application-Specific Integrated Circuits (ASIC)
Circuit Design
Verilog
Python (Programming Language)
C (Programming Language)
Assertion Based Verification
Cover Group Based Verification
Functional Verification
Logic Design
RTL Verification
Logic Synthesis
Clock Tree Synthesis
Stimulation
RTL Coding
Jeevan Gowda Summary
Jeevan Gowda, based in California, United States, is currently a Sr. Digital Engineer, ASIC Design Verification at Synaptics Incorporated. Jeevan Gowda brings experience from previous roles at Synaptics Incorporated, Western Digital and San Jose State University. Jeevan Gowda holds a 2018 - 2020 Master's degree in Electrical and Electronics Engineering @ San José State University. With a robust skill set that includes Static Timing Analysis, RTL Design, Universal Verification Methodology (UVM), Design, Debugging and more. Jeevan Gowda has 3 emails and 1 mobile phone numbers on RocketReach.
Looking for a different Jeevan Gowda?
Find contact details for 700 million professionals.