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Jeevan Gowda Location
California, United States
Jeevan Gowda Work
2025 -now Sr. Digital Engineer, ASIC Design Verification @
2023 -now ASIC Design Verification Engineer @
2021 -2023 Senior Electronic Design Engineer @
2021 -2021 Research Assistant @
2018 -2020 Graduate Student @
Jeevan Gowda Education
San Jose State University 2018-2020
Visvesvaraya Technological University 2013-2017
Jeevan Gowda Skills
Static Timing Analysis
RTL Design
Universal Verification Methodology (UVM)
Design
Debugging
Field-Programmable Gate Arrays (FPGA)
Application-Specific Integrated Circuits (ASIC)
Circuit Design
Verilog
Python (Programming Language)
C (Programming Language)
Assertion Based Verification
Cover Group Based Verification
Functional Verification
Logic Design
RTL Verification
Logic Synthesis
Clock Tree Synthesis
Stimulation
RTL Coding
Jeevan Gowda Summary
Jeevan Gowda, based in California, United States, is currently a Sr. Digital Engineer, ASIC Design Verification at Synaptics Incorporated. Jeevan Gowda brings experience from previous roles at Synaptics Incorporated, Western Digital and San Jose State University. Jeevan Gowda holds a 2018 - 2020 San Jose State University. With a robust skill set that includes Static Timing Analysis, RTL Design, Universal Verification Methodology (UVM), Design, Debugging and more. Jeevan Gowda has 3 emails and 1 mobile phone numbers on RocketReach.
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