Jayesh Pakhale Email & Phone Number
Staff ASIC Design Verification Engineer @ OLIX
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Jayesh Pakhale Location
- Austin, TX, US
Jayesh Pakhale Work
- 2026 -now Staff ASIC Design Verification Engineer @
- 2020 -2026 Senior ASIC Design Verification Engineer @
- 2011 -2020 Principal Design and Verification Engineer @
- 2010 -2011 Hardware Engineer @
- 2005 -2007 Hardware Design Engineer @ Entity Soltuions Limited
Jayesh Pakhale Education
- San Diego State University
Masters (Designed 32 bit RISC Processor using VHDL. Designed 32 point FFT Processor. Designed and Implemented FIR and IIR Fiter using VHDL and Matlab.)
2007-2009 - Nirma Institue of Technology, Gujarat University
Bachelor (Electronics and Communication)
2002-2005
Jayesh Pakhale Summary
- Jayesh Pakhale, based in Austin, TX, US, is currently a Staff ASIC Design Verification Engineer at OLIX. Jayesh Pakhale brings experience from previous roles at Amazon, SanDisk®, CareFusion and Entity Soltuions Limited. Jayesh Pakhale holds a 2007 - 2009 Masters in Designed 32 bit RISC Processor using VHDL. Designed 32 point FFT Processor. Designed and Implemented FIR and IIR Fiter using VHDL and Matlab. @ San Diego State University. Jayesh Pakhale has 2 emails and 1 mobile phone numbers on RocketReach.
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