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Jayanta Ghosh Location
Bengaluru, KA, IN
Jayanta Ghosh Work
Sr Manager Silicon Design Engineering @ (July 2025 - Present)
Manager Silicon Design Engineering @ (July 2022 - June 2025)
Member Of Technical Staff @ (July 2018 - June 2022)
Senior Design Engineer @ (July 2015 - June 2018)
Design Engineer 2 @ (August 2013 - June 2015)
Design Verification Engineer @ (May 2013 - August 2013)
Formal Verification Engineer @ (November 2010 - April 2013)
Jayanta Ghosh Education
JIS college of Engineering,WBUT
Bachelor of Technology (B.Tech.) (Electrical, Electronics and Communications Engineering)
2006-2010
Sodepur High School,West Bengal
(Science)
Jayanta Ghosh Skills
Assertion Based Verification
PSL
Perl
VHDL
Verilog
Debugging
SoC
System Verilog
OVM
Processors
Formal Verification
EDA
UVM
SystemVerilog
VLSI
Physical Design
ARM
Functional Verification
Jayanta Ghosh Summary
Jayanta Ghosh, based in Bengaluru, KA, IN, is currently a Sr Manager Silicon Design Engineering at AMD. Jayanta Ghosh brings experience from previous roles at AMD. Jayanta Ghosh holds a 2006 - 2010 Bachelor of Technology (B.Tech.) in Electrical, Electronics and Communications Engineering @ JIS college of Engineering,WBUT. With a robust skill set that includes Assertion Based Verification, PSL, Perl, VHDL, Verilog and more. Jayanta Ghosh has 3 emails and 1 mobile phone numbers on RocketReach.
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