Jayanta Ghosh Email & Phone Number
Sr Manager Silicon Design Engineering @ AMD
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Jayanta Ghosh Location
- Bengaluru, KA, IN
Jayanta Ghosh Work
- 2025 -now Sr Manager Silicon Design Engineering @
- 2022 -2025 Manager Silicon Design Engineering @
- 2018 -2022 Member Of Technical Staff @
- 2015 -2018 Senior Design Engineer @
- 2013 -2015 Design Engineer 2 @
- 2013 -2013 Design Verification Engineer @
- 2010 -2013 Formal Verification Engineer @
Jayanta Ghosh Education
- JIS college of Engineering,WBUT
Bachelor of Technology (B.Tech.) (Electrical, Electronics and Communications Engineering)
2006-2010 - Sodepur High School,West Bengal
(Science)
Jayanta Ghosh Skills
- Assertion Based Verification
- PSL
- Perl
- VHDL
- Verilog
- Debugging
- SoC
- System Verilog
- OVM
- Processors
- Formal Verification
- EDA
- UVM
- SystemVerilog
- VLSI
- Physical Design
- ARM
- Functional Verification
Jayanta Ghosh Summary
- Jayanta Ghosh, based in Bengaluru, KA, IN, is currently a Sr Manager Silicon Design Engineering at AMD. Jayanta Ghosh brings experience from previous roles at AMD. Jayanta Ghosh holds a 2006 - 2010 Bachelor of Technology (B.Tech.) in Electrical, Electronics and Communications Engineering @ JIS college of Engineering,WBUT. With a robust skill set that includes Assertion Based Verification, PSL, Perl, VHDL, Verilog and more. Jayanta Ghosh has 3 emails and 1 mobile phone numbers on RocketReach.
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