Jared Cheng Email & Phone Number
FPGA Design Engineer @ RADAR
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Jared Cheng Location
- Berkeley, CA, US
Jared Cheng Work
- FPGA Design Engineer @ (April 2025 - Present)
- Full Cycle FPGA Engineer @ (August 2023 - April 2025)
- FPGA Intern @ Raytheon Intelligence & Space (June 2022 - August 2022)
- Martin Group Undergraduate Research Assistant @ (January 2021 - May 2022)
- Space Technologies at Cal Quantum CubeSat Project Team Member @ (September 2020 - May 2022)
- Mars 2020 IDS Pipeline Intern @ (June 2021 - August 2021)
- Materials Project Diffraction Calculator Project @ Materials Project, UC Berkeley (September 2020 - June 2021)
Jared Cheng Education
- University of California, Berkeley
Bachelor of Applied Science - BASc (Materials Science and Engineering/Electrical Engineering and Computer Science)
2019-2023
Jared Cheng Skills
- Amazon Web Services (AWS)
- Atomic Force Microscopy
- C (Programming Language)
- C++
- Field-Programmable Gate Arrays (FPGA)
- Java
- KiCAD
- Mathematica
- Matplotlib
- Python (Programming Language)
- SystemVerilog
- ThermoCad
- Universal Verification Methodology (UVM)
- VHDL
- Verilog
- X-Ray Diffraction
Jared Cheng Summary
- Jared Cheng, based in Berkeley, CA, US, is currently a FPGA Design Engineer at RADAR. Jared Cheng brings experience from previous roles at Applied Signal Technology, Raytheon Intelligence & Space, Martin Group and Space Technologies At California (STAC). Jared Cheng holds a 2019 - 2023 Bachelor of Applied Science - BASc in Materials Science and Engineering/Electrical Engineering and Computer Science @ University of California, Berkeley. With a robust skill set that includes Amazon Web Services (AWS), Atomic Force Microscopy, C (Programming Language), C++, Field-Programmable Gate Arrays (FPGA) and more. Jared Cheng has 2 emails and 2 mobile phone numbers on RocketReach.
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