James Ayers Email & Phone Number
Analog Design Engineer @ Intel Corporation
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James Ayers Location
- Portland, OR, US
James Ayers Work
- Analog Design Engineer @ (July 2010 - Present)
- Student and Research Assistant @ (May 2002 - August 2010)
- Intern @ (June 2004 - March 2005)
- Intern @ (June 2003 - September 2003)
James Ayers Education
- Oregon State University
PhD (Electrical Engineering)
2004-2009 - Oregon State University
MS (Electrical Engineering)
2002-2004 - Oregon State University
BS (Electrical Engineering)
1997-2002
James Ayers Skills
- Analog
- Analog Circuit Design
- Cadence Virtuoso
- Circuit Design
- IC
- Integrated Circuit Design
- Low-power Design
- Mixed Signal
- RF
- VLSI
- Youth Mentoring
- Integrated Circuit
- Design
- Power
- Low Power Design
- Analog Design
James Ayers Summary
- James Ayers, based in Portland, OR, US, is currently a Analog Design Engineer at Intel. James Ayers brings experience from previous roles at Oregon State University, Intel and Intel Corporation. James Ayers holds a 2004 - 2009 PhD in Electrical Engineering @ Oregon State University. With a robust skill set that includes Analog, Analog Circuit Design, Cadence Virtuoso, Circuit Design, IC and more. James Ayers has 2 emails and 4 mobile phone numbers on RocketReach.
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