Jagadeesh G Email & Phone Number
Head of Platform Design , Silicon and System Validation @ Google
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Jagadeesh G Location
- California, United States
Jagadeesh G Work
- Head of Platform Design , Silicon and System Validation @ (September 2021 - Present)
- Director - Product Development and Test Engineering @ (September 2018 - September 2021)
- Sr Staff Engineer Manager: System Validation Engineering @ (January 2014 - January 2018)
- Staff Engineering Manager: Silicon Validation and Characterization @ (January 2011 - January 2014)
- Engineer | Sr Engineer : Product Development and characterization @ (January 2005 - January 2011)
- Product and Test Development @ (September 2002 - September 2004)
Jagadeesh G Education
- University of Idaho
PhD Student
2001-2004 - Western Michigan University
MS
- Jawaharlal Nehru Technological University
B.Tech
Jagadeesh G Skills
- ATE Characterization and Testing
- Cost reduction, test times and Yield.
- Cross-functional Team Leadership
- Hardware Development of Bench boards, ATE Load boards and Probe cards
- High speed Serial IO's USB2/USB3/UFS/PCIe/SATA/HDMI/MIPI DPHY/MIPI CPHY/Dispaly
- Offshore Team Leadership
- Product Engineering
- Production and Characterization Test methodologies
- SOC Charactarization and Qualification
Jagadeesh G Summary
- Jagadeesh G, based in California, United States, is currently a Head of Platform Design , Silicon and System Validation at Google. Jagadeesh G brings experience from previous roles at Qualcomm. Jagadeesh G holds a 2001 - 2004 PhD Student @ University of Idaho. With a robust skill set that includes ATE Characterization and Testing, Cost reduction, test times and Yield., Cross-functional Team Leadership, Hardware Development of Bench boards, ATE Load boards and Probe cards, High speed Serial IO's USB2/USB3/UFS/PCIe/SATA/HDMI/MIPI DPHY/MIPI CPHY/Dispaly and more. Jagadeesh G has 7 emails and 1 mobile phone numbers on RocketReach.
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