Jack Randall Location
- Austin, TX, US
Jack Randall Work
- 2016 - now Principal Engineer @
- 2013 - 2016 Architect @ Altera
- 2010 - 2012 Principal MTS @
- 2008 - 2010 MTS @
- 2005 - 2008 Engineering Manager @
- 2004 - 2005 Director of Engineering @
- 2003 - 2004 Professional Consultant @ Creeks Edge Technologies
- 2000 - 2003 Corporate Application Architect @ Silicon Metrics Corp.
- 1998 - 2000 Professional Services Consultant @
- 1997 - 1998 Corportate Staff Engineer @
- 1994 - 1996 Senior Member of the Technical Staff @
- 1993 - 1994 ASIC Consultant @ Rantec
- 1988 - 1993 Senior ASIC Designer @ Micral Inc.
- 1986 - 1988 Senior Electrical Engineer @ CPT Corp.
- 1984 - 1986 Electrical Engineer @
- 1982 - 1983 Software Engineer @
Jack Randall Education
- University of Minnesota
BS (Electrical Engineering)
1978 - 1983
Jack Randall Skills
- Functional Verification
- Development
- TCL
- Strategy
- VLSI
- FPGA
- EDA
- Physical Synthesis
- Processors
- Product Development
- Leadership
- Logic Design
- Management
- Engineering
- DFT
- CMOS
- RTL design
- Microsoft Word
- Logic Synthesis
- Intel
- Verilog
- History
- Semiconductors
- Marketing
- Primetime
- Integrated Circuit
- ASIC
- Floorplanning
- Physical Design
- Timing Closure
- Simulations
- Product R&d
- Testing
- Low Power Design
- SystemVerilog
- Static Timing Analysis
- IC
- Microsoft Office
- Mixed Signal
- Integrated Circuit Design
- Modeling
- Constraint Driven Apr
- SoC
- Microprocessors
- System On A Chip Soc
- System on a Chip
Jack Randall Summary
- Jack Randall, based in Austin, TX, US, is currently a Principal Engineer at Intel Corporation. Jack Randall brings experience from previous roles at Altera, AMD, Intrinsity and Intel Corp.. Jack Randall holds a 1978 - 1983 BS in Electrical Engineering @ University of Minnesota. With a robust skill set that includes Functional Verification, Development, TCL, Strategy, VLSI and more. Jack Randall has 3 emails and 2 mobile phone numbers on RocketReach.
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