Ivan Ratkovic Email

Ivan Ratkovic Skills

• Python
• Dct
• Power
• Cadence Virtuoso
• Computer Architecture
• Linux
• Field Programmable Gate Arrays Fpga
• Floating Point
• Verification And Validation V&V
• C
• Pin
• Rtl Compiler
• Embos
• System On A Chip Soc
• Ptpx
• Perl
• RTL design
• Matlab
• Magic
• Cacti
• Abel
• Gprof
• Low Power Techniques
• Scala
• Xilinx ISE
• Verilog
• Integrated Circuit Design
• Microcontrollers
• NCSim
• Design Verification Testing
• Cadence
• Scripting Bash
• TCL
• Cadence Encounter
• Signal Processing
• Pascal
• First Encounter
• LaTeX
• Programming
• Oprofile
• Java
• Power Optimization
• Embedded Systems
• Application Profiling
• Application Specific Integrated Circuits Asic
• FPGA
• RTL coding
• Cadence Rtl Compiler
• VCS
• VHDL
• EDA
• C++
• ModelSim
• PCB layout design
• Cadence Incisive
• Physical Synthesis
• Chisel
• Irsim
• Iir And Fir Filter Design
• Timing Closure
• SystemVerilog
• Synopsys tools
• Synopsys Tools Icc2
• Cadence Spectre
• Physical Design
• Power Estimation
• CPU design
• Research
• Static Timing Analysis
• Low Power Design
• Very Large Scale Integration Vlsi
• IAR Embedded Workbench
• RTOS
• Upf
• MSP430
• Power Analysis
• Riscv
• Field Programmable Gate Arrays
• Scripting
• Application Specific Integrated Circuits
• Very Large Scale Integration
• System on a Chip
• Verification and Validation