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Ivan Ratkovic Location
Belgrade, RS
Ivan Ratkovic Work
Chief Architect, CTO @ (March 2024 - Present)
Member Board Of Directors @ (December 2014 - Present)
SOC Power Architect, Power Manager @ (November 2021 - April 2024)
Senior Technical Staff, CPU Design and Verification @ (March 2017 - November 2021)
Co-Founder @ Hundo & VetGuide (October 2014 - January 2020)
Researcher @ (June 2013 - March 2017)
Researcher @ (October 2009 - March 2017)
Visiting Research Scholar @ Berkeley Wireless Research Center, UC Berkeley (January 2015 - May 2015)
Researcher @ ProSense FP7 project (October 2008 - June 2009)
Ivan Ratkovic Education
Universitat Politècnica de Catalunya
Doctor of Philosophy (PhD) (Computer Architecture)
2011-2016
Faculty of Electrical Engineering, University of Belgrade
MSc EE (Electronics)
2009-2011
Faculty of Electrical Engineering, University of Belgrade
Bsc EE (Electronics)
2003-2009
Ivan Ratkovic Skills
Application Profiling: pin, gprof, and oprofile
Application-Specific Integrated Circuits (ASIC)
C
C++
CADENCE (Encounter, RTL compiler, NCsim)
CPU design
Chisel
Computer Architecture
Design Verification Testing
EDA
Embedded Systems
Energy Efficiency
FPGA
Field-Programmable Gate Arrays (FPGA)
Floating point
IAR Embedded Workbench
IIR and FIR filter design
Integrated Circuit Design
Integrated Circuits (IC)
Java
LaTeX
Linux
Low Power Techniques
Low-power Design
MSP430
Management
Matlab
Microcontrollers
Microprocessors
PCB layout design
Pascal
Physical Design
Physical Synthesis
Power Analysis
Power Estimation
Power Management
Power Optimization
Program Management
Project Management
Proposal Generation
RISCV
RTL design
RTOS
Research
Scala
Scripting (bash, tcl, python, perl)
Signal Processing
Silicon Bringup
Silicon Characterization
Static Timing Analysis
Synopsys Tools (ICC2, DCT, VCS, PTPX)
System on a Chip (SoC)
SystemVerilog
Team Leadership
Technical Leadership
Tensor Processing Unit
Timing Closure
UPF
VHDL
Vector Processing Unit
Verification and Validation (V&V)
Verilog
Very-Large-Scale Integration (VLSI)
embOS
Python
Dct
Power
Cadence Virtuoso
Field Programmable Gate Arrays Fpga
Verification And Validation V&V
Pin
Rtl Compiler
System On A Chip Soc
Ptpx
Perl
Magic
Cacti
Abel
Gprof
Xilinx ISE
NCSim
Cadence
Scripting Bash
TCL
Cadence Encounter
First Encounter
Programming
Oprofile
Application Profiling
Application Specific Integrated Circuits Asic
RTL coding
Cadence Rtl Compiler
VCS
ModelSim
Cadence Incisive
Irsim
Synopsys tools
Synopsys Tools Icc2
Cadence Spectre
Low Power Design
Very Large Scale Integration Vlsi
Field Programmable Gate Arrays
Scripting
Application Specific Integrated Circuits
Very Large Scale Integration
System on a Chip
Verification and Validation
Ivan Ratkovic Summary
Ivan Ratkovic, based in Belgrade, RS, is currently a Chief Architect, CTO at Chipfy. Ivan Ratkovic brings experience from previous roles at ELITAS d.o.o., Esperanto Technologies, Inc and Hundo & VetGuide. Ivan Ratkovic holds a 2011 - 2016 Doctor of Philosophy (PhD) in Computer Architecture @ Universitat Politècnica de Catalunya. With a robust skill set that includes Application Profiling: pin, gprof, and oprofile, Application-Specific Integrated Circuits (ASIC), C, C++, CADENCE (Encounter, RTL compiler, NCsim) and more. Ivan Ratkovic has 2 emails on RocketReach.
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