Iris Miao Email & Phone Number
ASIC Design Engineer @ Google
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Iris Miao Location
- Rancho Palos Verdes, CA, US
Iris Miao Work
- 2022 -now ASIC Design Engineer @
- 2020 -2022 ASIC Design Engineer @
- 2018 -2020 Senior FPGA Design Engineer @
- 2012 -2018 Design and Verification Engineer @
- 2008 -2011 ASIC Engineer @
- 2006 -2008 ASIC Designer @
- 2005 -2006 ASIC Engineer @
- 2004 -2005 Senior ASIC Engineer @
- 2000 -2004 ASIC Engineer @
Iris Miao Education
- University of Toledo
Master of Electrical Engineering
1998-1999
Iris Miao Skills
- RTL design
- SystemVerilog
- ARM
- Design
- ASIC
- AMBA AHB
- Static Timing Analysis
- Application Specific Integrated Circuits Asic
- Telecommunications
- RTL coding
- SoC
- Verilog
- FPGA
- VLSI
- NCSim
- EDA
- Functional Verification
- Debugging
- Timing Closure
- IC
- Application Specific Integrated Circuits
Iris Miao Summary
- Iris Miao, based in Rancho Palos Verdes, CA, US, is currently a ASIC Design Engineer at Google. Iris Miao brings experience from previous roles at Qualcomm, Boeing and Conexant. Iris Miao holds a 1998 - 1999 Master of Electrical Engineering @ University of Toledo. With a robust skill set that includes RTL design, SystemVerilog, ARM, Design, ASIC and more. Iris Miao has 3 emails and 2 mobile phone numbers on RocketReach.
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