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Howard Chou Location
San Jose, CA, US
Howard Chou Work
2025 -now Senior Design Verification Manager @
2015 -2025 Senior Design Verification Manager @
2004 -2015 Design Engineer, Senior Member of Technical Staff @ Altera
2000 -2004 Senior Design Engineer @
Howard Chou Education
University of Toronto
Master of Applied Science (M.A.Sc) (Electrical Engineering)
1998-2000
University of Toronto
Bachelor of Applied Science (B.A.Sc.) (Engineering Science)
1994-1998
Howard Chou Skills
FPGA
SRAM
Circuit Design
RTL Design
Functional Verification
Lint
Static Timing Analysis
UVM
Conformal LEC
HSIM
OPUS
Perl
Verilog
SPICE
C Programming Language
Gate Level Simulation
System On A Chip Soc
Verdi
SystemVerilog
Assertions
Code Coverage
System on a Chip
C (Programming Language
Howard Chou Summary
Howard Chou, based in San Jose, CA, US, is currently a Senior Design Verification Manager at Altera. Howard Chou brings experience from previous roles at Intel Corporation, Altera and Lattice Semiconductor. Howard Chou holds a 1998 - 2000 Master of Applied Science (M.A.Sc) in Electrical Engineering @ University of Toronto. With a robust skill set that includes FPGA, SRAM, Circuit Design, RTL Design, Functional Verification and more. Howard Chou has 3 emails and 1 mobile phone numbers on RocketReach.
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