Hock Tan Email & Phone Number
PMTS Silicon Design Engineer @ AMD
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Hock Tan Location
- San Jose, CA, US
Hock Tan Work
- 2025 -now PMTS Silicon Design Engineer @
- 2015 -2024 EDA Director @
- 2012 -2015 Sr CAD Manager @
- 2002 -2012 Sr Staff Application Consultant @
- 2000 -2002 Application Engineer @
- 1997 -2000 Student @ UMIST
Hock Tan Education
- UMIST 1997-1999
- Singapore Polytechnic 1990-1993
Hock Tan Skills
- EDA
- Physical Design
- SoC
- Mixed Signal
- Static Timing Analysis
- ASIC
- Physical Verification
- Logic Synthesis
- FPGA
- TCL
- Timing Closure
- Management
- Integrated Circuit Design
- Debugging
- Signal Integrity
- IC
- Semiconductors
- VLSI
- Parasitic Extraction
- LVS
- DRC
- People Skills
- Verilog
- RTL design
- UPF
- CPF
- IEEE 1801
- Synopsys Primetime
- Synopsys IC Compiler
- Synopsys IC Validator
- Synopsys Star-RCXT
- Synopsys HSPICE
- Synopsys PrimeRail
- Synopsys Milkyway
- Synopsys Design Compiler
- Cadence EPS
- Cadence Voltus
- Cadence VPS
- Cadence QRC
- Cadence Virtuoso
- Cadence EDI
- Cadence RTL Compiler
- Cadence Encounter Test
- Cadence Conformal
- Mentor Calibre
- Mentor DFTA
- Mentor TestKompress
- Mentor Vista
- Atrenta Spyglass
- ClioSoft
- Leadership
- Research
- SQL
- CAD
- Synopsys Star Rcxt
- Lattice
- Support
- Development
- Sales
- Strategy
- Public Speaking
- Sales Support
- Microsoft Excel
Hock Tan Summary
- Hock Tan, based in San Jose, CA, US, is currently a PMTS Silicon Design Engineer at AMD. Hock Tan brings experience from previous roles at Lattice Semiconductor, Synopsys and Avanti Corporation. Hock Tan holds a 1997 - 1999 UMIST. With a robust skill set that includes EDA, Physical Design, SoC, Mixed Signal, Static Timing Analysis and more. Hock Tan has 3 emails and 1 mobile phone numbers on RocketReach.
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