Hin Chan Email
SMTS Design Verification Engineer @ AMD
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Hin Chan Location
- Canada
Hin Chan Work
- SMTS Design Verification Engineer @ (August 2010 - Present)
- Sr Verification Engineer @ Actel (July 2005 - August 2010)
Hin Chan Education
- University of Toronto
BASc (Engineering Science - Electrical)
2000-2005
Hin Chan Skills
- ASIC
- Debugging
- EDA
- Embedded Systems
- FPGA
- Functional Verification
- IC
- ModelSim
- Perl
- Semiconductors
- Simulations
- SoC
- SystemVerilog
- TCL
- VHDL
- VLSI
- Verilog
Hin Chan Summary
- Hin Chan, based in Canada, is currently a SMTS Design Verification Engineer at AMD. Hin Chan brings experience from previous roles at Actel. Hin Chan holds a 2000 - 2005 BASc in Engineering Science - Electrical @ University of Toronto. With a robust skill set that includes ASIC, Debugging, EDA, Embedded Systems, FPGA and more. Hin Chan has 2 emails on RocketReach.
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