Hetali Patel Email & Phone Number
Pre-Silicon Verification Engineer @ Intel Corporation
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Hetali Patel Location
- Santa Clara, CA, US
Hetali Patel Work
- Pre-Silicon Verification Engineer @ (April 2018 - Present)
- Hardware Verification Engineer @ (October 2013 - April 2018)
Hetali Patel Education
- University of Southern California
Master's degree (Electrical Engineering (VLSI & Computer Architecture))
2011-2013
Hetali Patel Skills
- ASIC Design & Verification
- Computer Architecture
- Coverage-Driven Verification
- DSP Integration (Tensilica)
- Firmware Bring-up (C/Assembly)
- Memory Subsystems (SRAM, Cache, ECC)
- Pre-Silicon Verification
- Regression Debugging
- SMMU / MMU
- SoC Integration
- Synopsys tools
- SystemVerilog
- SystemVerilog / UVM
- Unix
- Verilog
Hetali Patel Summary
- Hetali Patel, based in Santa Clara, CA, US, is currently a Pre-Silicon Verification Engineer at Intel Corporation. Hetali Patel brings experience from previous roles at MIPS. Hetali Patel holds a 2011 - 2013 Master's degree in Electrical Engineering (VLSI & Computer Architecture) @ University of Southern California. With a robust skill set that includes ASIC Design & Verification, Computer Architecture, Coverage-Driven Verification, DSP Integration (Tensilica), Firmware Bring-up (C/Assembly) and more. Hetali Patel has 3 emails and 1 mobile phone numbers on RocketReach.
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